The present invention generally relates to a sense amplifier (amp) connected to a memory cell transistor, and more particularly to a sense amp that reads the information stored in the memory cell transistor based on the difference in the threshold of the memory cell transistor.
Electrically Erasable and Programmable ROM (EEPROM) is available as an example of a single memory cell transistor. Each memory cell transistor has a double gate structure consisting of a floating gate and a control gate. When data is written to the memory cell transistor, hot electrons generated in the drain region are accelerated and injected into the floating gate. A difference arises between the operating characteristics of the memory cell transistor that injects electric charge into the floating gate and those of the memory cell transistor that does not inject electric charge into the floating gate. Data is read by detecting this difference.
FIG. 1 is a schematic circuit diagram illustrating a conventional sense amp 100, and FIG. 2 is an operating waveform diagram of the sense amp 100. The sense amp 100 determines the threshold of a memory cell transistor 105 based on the potential of a bit line.
The sense amp 100 comprises a differential amp 101, a P-channel type MOS transistor 102, an N-channel type MOS transistor 103, and a CMOS inverter 104. The transistor 102 is used as a read load and has a gate, a drain connected to the gate, and a source connected to a high potential power supply. The transistor 103 is connected between the drain of the transistor 102 and a bit line 106. The inverter 104 has an input terminal connected to the bit line 106 and an output terminal connected to the gate of the transistor 103. The differential amp 101 has an inverted input connected to the drain of the transistor 102, and a noninverted input connected to a reference potential Vref. The differential amp 101 outputs an output signal C indicating the determination result of the threshold of the memory cell transistor 105.
The memory cell transistor 105 changes its own threshold in accordance with the amount of electric charge stored in the floating gate. Desired data is stored in the memory cell transistor 105 by associating the change of threshold with storage data. In the read operation, the memory cell transistor 105 is selectively connected between the bit line 106 and the ground, and a selection signal LS is applied to the control gate.
In the initial state, the memory cell transistor 105 is nonselective (the control gate is off), and the bit line 106 is set to the ground potential. In such a state, as shown in FIG. 2, the power supply is started up at time t0. Thereupon, the drain potential Va of the transistor 102 rises up near to the power supply potential. The transistor 103 then goes on in response to the initial output startup of the inverter 104, and the potential VBL of the bit line 106 also rises together with the drain potential Va. When the inverter 104 slowly starts inversion as the potential VBL of the bit line 106 rises, the transistor 103 proceeds to the off state, and the potential VBL of the bit line 106 slowly rises. When a specific time L elapses from the power supply startup, the drain potential Va of the transistor 102 becomes stable. The potential Va after the transistor 102 has become stable is set to a higher potential than the threshold of the inverter 104 only for the threshold of the transistor 103. Thus the initial setup operation is completed.
After the initial setup has been completed, the selection signal LS is turned on and the control gate of the memory cell transistor 105 is turned on. Thereupon, the memory cell transistor 105 goes on or off according to the threshold. In other words, if the threshold of the memory cell transistor 105 is lower than the value of the selection signal LS, the memory cell transistor 105 goes on and the potential VBL of the bit line 106 decreases. If the threshold of the memory cell transistor 105 is higher than the value of the selection signal LS, the memory cell transistor 105 goes off and the potential VBL of the bit line 106 is maintained at a constant level.
When the memory cell transistor 105 goes on, the degree of drop in the potential VBL of the bit line 106 is determined based on the balance between the drive capacity of the memory cell transistor 105 and the drive capacities of the transistors 102 and 103. The drain potential Va of the transistor 102 also decreases together with the potential VBL of the bit line 106. The differential amp 101 compares the reference potential Vref and potential Va and detects the variation of the potential Va. The reference potential Vref is set within the variation range of the potential Va.
In the sense amp 100, as the drive capacity of the transistor 102 on the power supply side is set low, the variation of the drain potential Va increases and the sensitivity of the sense amp improves. However, if the drive capacity of the transistor 102 is set low, the current supplied to the bit line 106 through the transistor 103 when the power goes on is reduced. Accordingly, the time before the drain potential Va becomes stable (i.e., the initial setup time) is prolonged. As a result, the startup of the sense amp 100 is delayed, thereby impeding high-speed operation.
It is an object of the present invention to provide a sense amp with improved sensitivity and that is suitable for high-speed operation.
In one aspect of the invention, a sense amp is described for supplying a current to a bit line connected to a first potential through a memory cell transistor and detecting a potential of the bit line. The potential varies according to a conductive state of the memory cell transistor. The sense amp includes a load element and a first transistor connected in series between a second potential and the bit line. A second transistor is connected between the second potential and the bit line. The second transistor has a higher threshold than the first transistor. An inverter has an input terminal connected to the bit line and an output terminal connected to the gates of the first and second transistors. A differential amp has a first input terminal connected between the load element and the first transistor, a second input terminal connected to a reference potential, an output terminal that outputs a signal indicating the potential detection result of the bit line.
In another aspect of the invention, a sense amp is described for supplying a current to a bit line connected to a first potential through a memory cell transistor and detecting a potential of the bit line. The potential varies according to a conductive state of the memory cell transistor. The sense amp includes a load element and a first transistor connected in series between the second potential and the bit line. A second transistor is connected between a second power supply and the bit line. A first inverter has an input terminal connected to the bit line and an output terminal connected to the gate of the first transistor. A second inverter has an input terminal connected to the bit line and an output terminal connected to the gate of the second transistor. The second inverter has a lower threshold than the first inverter. A differential amp has a first input terminal connected to a node between the load element and the first transistor, a second input terminal connected to a reference potential, and an output terminal that outputs a signal indicating the potential detection result of the bit line.
In yet another aspect of the invention, a sense amp is described for supplying a current to a bit line connected to a first potential through a memory cell transistor and detecting a potential of the bit line. The potential varies according to a conductive state of the memory cell transistor. The sense amp includes a load element and a first transistor connected in series between a second potential and the bit line. A second transistor is connected between the second potential and the bit line. A switching transistor is connected between the second potential and the second transistor. An inverter has an input terminal connected to the bit line and an output terminal connected to the gates of the first and second transistors. A differential amp has a first input terminal connected to a node between the load element and the first transistor, a second input terminal connected to a reference potential, and an output terminal that outputs a signal indicating the potential detection result of the bit line.
In one aspect of the invention, a sense amp is described for supplying current to a bit line connected to a memory cell transistor and detecting a potential of the bit line. The potential varies according to a conductive state of the memory cell transistor. The sense amp includes a load element and a first transistor. The load element and the first transistor are connected in series between a first potential and the bit line. A second transistor is connected between the first potential and the bit line. The second transistor turns on when a current is supplied to the bit line. A first inverter has an input terminal connected to the bit line and an output terminal connected to a gate of the first transistor. A differential amp has a first input terminal connected to a reference potential, a second input terminal connected to a node between the load element and the first transistor, and an output terminal that outputs a signal indicating a difference between the reference potential and the bit line potential.
Other aspects and advantages of the invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example of the principles of the invention.